1. Field of the Invention
The present invention relates to a semiconductor device having wires attached to a semiconductor chip, and encapsulated with resin.
2. Description of the Background Art
As to packages having output terminals arranged in four directions along the four sides of a rectangle such as a QFP (Quad Flat Package) and BGA (Ball Grid Array), the bonding pads on a semiconductor chip are arranged along the edge of the four sides of a rectangle. By such a structure, electrical connection can be established through wire bonding between an output terminal and a bonding pad on a semiconductor chip without crossing of wires (fine metal wires).
The structure having bonding pads arranged along the four sides is disadvantageous in that the dead space between the bonding pads and the like cannot be obviated. It was difficult to reduce the chip size. In the above-described structure, fine wires must be routed from an active part in the chip to a region in the periphery of the chip (bonding pad site), causing the problem of signal delay, noise, and the like. A burden is laid on the chip designer to avoid such problems. In order to establish wiring up to a bonding pad in the above-described structure, the active part must be divided or reallocated. Therefore, redesigning of a chip is required when a new device is to be developed even though there is a chip that can serve as the base. The load on the task in chip designing was significantly increased.
In view of the foregoing, there are proposed a semiconductor device having electrode pads on a semiconductor chip aggregated along one side (refer to Japanese Patent Laying-Open No. 2001-156107), a semiconductor device employing an LOC (Lead Over Chip) structure in which electrode pads are arranged in an H shape on a semiconductor chip with lead terminals at the longer side placed on a semiconductor chip region (refer to Japanese Patent Laying-Open No. 10-242373), and a semiconductor device having the lead and chip provided at different heights with a row of electrode pads aggregated at the center of the semiconductor chip (refer to Japanese Patent Laying-Open No. 2001-156237), and the like.
The number of electrode pads and the number of inner leads must be increased when there are more electrical signals to be transferred at one reflecting the increase in the degree of integration of semiconductor devices. There is a limit in reducing the size of a semiconductor device in which the number of sides where inner leads can be arranged is restricted as set forth above. If more inner leads are arranged along the limited sides in accordance with the increase of electrode pads and inner leads, each inner lead will become so small that defects such as inner lead deformation occurs. It was therefore necessary to set the dimension of the inner lead with a limit in size reduction.